SEPICA Level 1 Data Structures



s3_shk1.h , v 1.2

#include "hdfi.h"

struct sshshk1{
	uint32 sctime_readout;	/* first minor frame of readout cycle, */
	                        /* 32 bit spacecraft clock time */
	float64 sctime_collection; /* time of the start of the first spin in the */
	                           /* 5-spin cycle. sub-second resolution */

	uint32 QAC; /* number of missing minor frames in the 5-spin cycle  */

	uint8 HKSECTOR;	/* Housekeeping Sector    */
	uint8 P5I;	/* +5V I    */
	uint8 M5I;	/* -5V I    */
	uint8 P15I;	/* +15V I    */
	uint8 M15I;	/* -15V I    */
	uint8 P5V;	/* +5V     */
	uint8 M5V;	/* -5V     */
	uint8 P15V;	/* +15V     */
	uint8 M15V;	/* -15V     */
	uint8 _30KI;	/* 30kV I    */
	uint8 _30KV;	/* 30kV     */
	uint8 _2KI;	/* 2kV I    */
	uint8 _2KV;	/* 2kV     */
	uint8 _75I;	/* 75V I    */
	uint8 _75V;	/* 75V     */
	uint8 P5T;	/* +/-5V Temp.    */
	uint8 P15T;	/* +/-15V Temp.    */
	uint8 _2KAV;	/* 2kV A    */
	uint8 _2KBV;	/* 2kV B    */
	uint8 _2KCV;	/* 2kV C    */
	uint8 VAL1I;	/* Valve PC 1 I  */
	uint8 VAL2I;	/* Valve PC 2 I  */
	uint8 VAL3I;	/* Valve PC 3 I  */
	uint8 VAL1V;	/* Valve PC 1 V  */
	uint8 VAL2V;	/* Valve PC 2 V  */
	uint8 VAL3V;	/* Valve PC 3 V  */
	uint8 BASET;	/* Base Temp.    */
	uint8 SSD1T;	/* SSD 1 Temp.   */
	uint8 SSD2T;	/* SSD 2 Temp.   */
	uint8 SSD3T;	/* SSD 3 Temp.   */
	uint8 TANKT;	/* Tank Temp.    */
	uint8 EBOXT;	/* E-box Temp.    */
	uint8 HV30T;	/* HV Temp.    */
	uint8 COLLT;	/* Collimator Temp.    */
	uint8 PC1T;	/* PC 1 Temp.   */
	uint8 PC2T;	/* PC 2 Temp.   */
	uint8 PC3T;	/* PC 3 Temp.   */
	uint8 GRMT;	/* GRM Temp.    */
};

s3_shk2.h , v 1.2

#include "hdfi.h"

struct sshshk2{
	uint32 sctime_readout;	/* first minor frame of readout cycle, */
	                        /* 32 bit spacecraft clock time */
	float64 sctime_collection; /* time of the start of the first spin in the */
	                           /* 5-spin cycle. sub-second resolution */

	uint32 QAC; /* number of missing minor frames in the 5-spin cycle  */

	uint8 HKSECTOR;	/* Housekeeping Sector    */
	uint8 FILL1;	/* Fill Time PC 1  */
	uint8 FILL2;	/* Fill Time PC 2  */
	uint8 FILL3;	/* Fill Time PC 3  */
	uint8 POWERS;	/* Power Status    */
	uint8 RELAYS;	/* Relay Status    */
	uint8 OVERI;	/* Over Currents    */
	uint8 P15LIM;	/* +15V Current Limit   */
	uint8 M15LIM;	/* -15V Current Limit   */
	uint8 P5LIM;	/* +5V Current Limit   */
	uint8 M5LIM;	/* -5V Current Limit   */
	uint8 _30KSTATH;	/* 30kV Discharge    */
	uint8 _30KSET;	/* 30kV Set Value   */
	uint8 _30KSTATL;	/* 30kV Plug Status   */
	uint8 _2KASTATH;	/* 2kV A Discharge   */
	uint8 _2KASET;	/* 2kV A Set Value  */
	uint8 _2KASTATL;	/* 2kV A Plug Status  */
	uint8 _2KBSTATH;	/* 2kV B Discharge   */
	uint8 _2KBSET;	/* 2kV B Set Value  */
	uint8 _2KBSTATL;	/* 2kV B Plug Status  */
	uint8 _2KCSTATH;	/* 2kV C Discharge   */
	uint8 _2KCSET;	/* 2kV C Set Value  */
	uint8 _2KCSTATL;	/* 2kV C Plug Status  */
	uint8 _75STATH;	/* 75V Discharge    */
	uint8 _75SET;	/* 75V Set Value   */
	uint8 _75STATL;	/* 75V Plug Status   */
	uint16 PC1P;	/* PC 1 Pres.   */
	uint16 PC2P;	/* PC 2 Pres.   */
	uint16 PC3P;	/* PC 3 Pres.   */
	uint16 LINEP;	/* line Pres.    */
	uint8 PC1O;	/* PC 1 On/Off   */
	uint8 PC2O;	/* PC 2 On/Off   */
	uint8 PC3O;	/* PC 3 On/Off   */
	uint8 ALARMS;	/* Alarm Flags    */
};

s3_shk3.h , v 1.2

#include "hdfi.h"

struct sshshk3{
	uint32 sctime_readout;	/* first minor frame of readout cycle, */
	                        /* 32 bit spacecraft clock time */
	float64 sctime_collection; /* time of the start of the first spin in the */
	                           /* 5-spin cycle. sub-second resolution */

	uint32 QAC; /* number of missing minor frames in the 5-spin cycle  */

	uint8 HKSECTOR;	/* Housekeeping Sector    */
	uint8 FAN1MODE;	/* Fan 1 Mode   */
	uint8 FAN1BASE;	/* Fan 1 Baseline Subtr.  */
	uint8 FAN1LOGIC;	/* Fan 1 SSD Logic  */
	uint8 FAN1PCY;	/* Fan 1 Valid PC  */
	uint8 FAN1PCZ;	/* Fan 1 Valid PC  */
	uint8 FAN1SSD;	/* Fan 1 Valid SSD  */
	uint8 FAN1BANK;	/* Fan 1 Memory Bank  */
	uint8 FAN1BLOCK;	/* Fan 1 Memory Block  */
	uint8 FAN1DATA;	/* Fan 1 Data Selected  */
	uint8 FAN2MODE;	/* Fan 2 Mode   */
	uint8 FAN2BASE;	/* Fan 2 Baseline Subtr.  */
	uint8 FAN2LOGIC;	/* Fan 2 SSD Logic  */
	uint8 FAN2PCY;	/* Fan 2 Valid PC  */
	uint8 FAN2PCZ;	/* Fan 2 Valid PC  */
	uint8 FAN2SSD;	/* Fan 2 Valid SSD  */
	uint8 FAN2BANK;	/* Fan 2 Memory Bank  */
	uint8 FAN2BLOCK;	/* Fan 2 Memory Block  */
	uint8 FAN2DATA;	/* Fan 2 Data Selected  */
	uint8 FAN3MODE;	/* Fan 3 Mode   */
	uint8 FAN3BASE;	/* Fan 3 Baseline Subtr.  */
	uint8 FAN3LOGIC;	/* Fan 3 SSD Logic  */
	uint8 FAN3PCY;	/* Fan 3 Valid PC  */
	uint8 FAN3PCZ;	/* Fan 3 Valid PC  */
	uint8 FAN3SSD;	/* Fan 3 Valid SSD  */
	uint8 FAN3BANK;	/* Fan 3 Memory Bank  */
	uint8 FAN3BLOCK;	/* Fan 3 Memory Block  */
	uint8 FAN3DATA;	/* Fan 3 Data Selected  */
};

s3_shk4.h , v 1.2

#include "hdfi.h"

struct sshshk4{
	uint32 sctime_readout;	/* first minor frame of readout cycle, */
	                        /* 32 bit spacecraft clock time */
	float64 sctime_collection; /* time of the start of the first spin in the */
	                           /* 5-spin cycle. sub-second resolution */

	uint32 QAC; /* number of missing minor frames in the 5-spin cycle  */

	uint8 HKSECTOR;	/* Housekeeping Sector    */
	uint8 PC1YTH;	/* PC 1 Y Threshold  */
	uint8 PC1ZTH;	/* PC 1 Z Threshold  */
	uint8 PC2YTH;	/* PC 2 Y Threshold  */
	uint8 PC2ZTH;	/* PC 2 Z Threshold  */
	uint8 PC3YTH;	/* PC 3 Y Threshold  */
	uint8 PC3ZTH;	/* PC 3 Z Threshold  */
	uint8 SSD1TH;	/* SSD 1 Threshold   */
	uint8 BIT1PERIOD;	/* BIT 1 Period   */
	uint8 SSD2TH;	/* SSD 2 Threshold   */
	uint8 BIT2PERIOD;	/* BIT 2 Period   */
	uint8 SSD3TH;	/* SSD 3 Threshold   */
	uint8 BIT3PERIOD;	/* BIT 3 Period   */
	uint8 DEDX1TH;	/* dEdX 1 Threshold   */
	uint8 DEDX2TH;	/* dEdX 2 Threshold   */
	uint8 DEDX3TH;	/* dEdX 3 Threshold   */
	uint8 DET1TRIG;	/* CAMEX 1 Trigger   */
	uint8 DET1EVENT;	/* Valid Event 1 Condition  */
	uint8 DET1GAIN;	/* SSD 1 CAMEX Gain  */
	uint16 DET1CHANNELS;	/* BIT 1 Channels   */
	uint8 DET2TRIG;	/* CAMEX 2 Trigger   */
	uint8 DET2EVENT;	/* Valid Event 2 Condition  */
	uint8 DET2GAIN;	/* SSD 2 CAMEX Gain  */
	uint16 DET2CHANNELS;	/* BIT 2 Channels   */
	uint8 DET3TRIG;	/* CAMEX 3 Trigger   */
	uint8 DET3EVENT;	/* Valid Event 3 Condition  */
	uint8 DET3GAIN;	/* SSD 3 CAMEX Gain  */
	uint16 DET3CHANNELS;	/* BIT 3 Channels   */
	uint16 ACTRCTRL;	/* ACTR Control Register   */
	uint8 FANPRIOR; /* Fan Priority    */
	uint16 ACTRSAMPLE;      /* ACTR Sample Register   */
};

s3_shk5.h , v 1.2

#include "hdfi.h"

struct sshshk5{
	uint32 sctime_readout;	/* first minor frame of readout cycle, */
	                        /* 32 bit spacecraft clock time */
	float64 sctime_collection; /* time of the start of the first spin in the */
	                           /* 5-spin cycle. sub-second resolution */

	uint32 QAC; /* number of missing minor frames in the 5-spin cycle  */

	uint8 HKSECTOR;	/* Housekeeping Sector    */

	uint8 ALARMOP3;	/* Overpressure Fan 3   */
	uint8 ALARMOP2;	/* Overpressure Fan 2   */
	uint8 ALARMOP1;	/* Overpressure Fan 1   */
	uint8 ALARMUP3;	/* Underpressure Fan 3   */
	uint8 ALARMUP2;	/* Underpressure Fan 2   */
	uint8 ALARMUP1;	/* Underpressure Fan 1   */
	uint8 ALARMDISCHG;	/* Discharge Alarm    */
	uint8 ALARM30KI;	/* 30kV I Alarm   */
	uint8 ALARM30KV;	/* 30kV Alarm    */
	uint8 ALARM2KVC;	/* 2kV C Alarm   */
	uint8 ALARM2KVB;	/* 2kV B Alarm   */
	uint8 ALARM2KVA;	/* 2kV A Alarm   */
	uint8 ALARM2KI;	/* 2kV I Alarm   */
	uint8 ALARM2KV;	/* 2kV Alarm    */
	uint8 ALARM75I;	/* 75V I Alarm   */
	uint8 ALARM75V;	/* 75V Alarm    */
	uint8 ALARMM15I;	/* -15V I Alarm   */
	uint8 ALARMM15V;	/* -15V Alarm    */
	uint8 ALARMP15I;	/* +15V I Alarm   */
	uint8 ALARMP15V;	/* +15V Alarm    */
	uint8 ALARMM5I;	/* -5V I Alarm   */
	uint8 ALARMM5V;	/* -5V Alarm    */
	uint8 ALARMP5I;	/* +5V I Alarm   */
	uint8 ALARMP5V;	/* +5V Alarm    */
};

s3_smatrix.h , v 1.6

#include "hdfi.h"

#define SMAT_N     60  /* number of matrix rate channels */
#define SMAT_S     1  /* number of sectors */
#define SMAT_CYC   6  /* number of cycles per SR = 60 / 10 */

 /* total size (in bytes) of SMAT data (including slack) in a full SR */
#define SMAT_TSZ   540 

/* size (in bytes) of SMAT cycle (including slack) */
#define SMAT_CSZ   SMAT_TSZ/SMAT_CYC 
#define SMAT_ESZ   SMAT_TSZ/60  /* size (in bytes) of SMAT area in EDB */

/* Matrix rates are collected over 10 spins and output during the next */
/* 10 spins(or edb's). There are 6 matrix rate collection cycles per */
/* Science Record */

/* sctime_readout: spacecraft clock of first minor frame of the */
/* first edb of the matrix rate output cycle */

/* sctime_collection:  time of the start of the first spin in the */
/* collection cycle, in spacecraft clock time units */

/* smatrix structure contains SEPICA matrix rates for 1 10-spin collection cycle */

struct smatrix{
   uint32 sctime_readout;  /* 32 bit spacecraft time  */
   float64 sctime_collection; /* spacecraft time, sub-second resolution */
   uint32 QAC;     /* number of missing frames in this 10-spin cycle */

   uint16 MATRIX[SMAT_N]; /* 49 Matrix rates, 11 fill */
};


s3_smonitor.h , v 1.6

#include "hdfi.h"

#define SMON_N     12  /* number of monitor rates */
#define SMON_S     8  /* number of sectors */
#define SMON_CYC   12  /* number of cycles per SR = 60 / 5 */
#define SMON_NFILL 4  /* amount of fill data elements */

 /* total size (in bytes) of SMON data (including slack) in a full SR */
#define SMON_TSZ   1800 

 /* size (in bytes) of SMON cycle (including slack) */
#define SMON_CSZ   SMON_TSZ/SMON_CYC 
#define SMON_ESZ   SMON_TSZ/60  /* size (in bytes) of SMON in EDB */

/* monitor rates are collected over 5 spins and output during the next */
/* 5 spins(or edb's). There are 12 matrix rate collection cycles per */
/* Science Record */

/* sctime_readout: spacecraft clock of first minor frame of the */
/* first edb of the monitor rate output cycle */

/* sctime_collection:  time of the start of the first spin in the */
/* collection cycle, in spacecraft clock time units */

struct smonitor{

   uint32 sctime_readout;     /* 32 bit spacecraft time  */
   float64 sctime_collection; /* spacecraft time, sub-second resolution */
   uint32 QAC;	/* number of missing frames in this 5-spin cycle */

   uint16 MONITOR[SMON_N][SMON_S];/* 12 Monitor rates, 8 sectors */
   uint16 FILL[SMON_NFILL];    /* Fill  data   */
};

s3_ssector.h , v 1.5

#include "hdfi.h"

#define SSEC_N     20  /* number of matrix rates */
#define SSEC_S     8  /* number of sectors */
#define SSEC_CYC   6  /* number of cycles per SR = 60 / 10 */

 /* total size (in bytes) of SMON data (including slack) in a full SR */
#define SSEC_TSZ   1440  

 /* size (in bytes) of SSEC cycle (including slack) */
#define SSEC_CSZ   SSEC_TSZ/SSEC_CYC 

#define SSEC_ESZ   SSEC_TSZ/60  /* size (in bytes) of SSEC area in EDB */

/* Sectored rates are collected over 10 spins and output during the next */
/* 10 spins (or edb's). There are 6 sectored rate collection cycles per */
/* Science Record */

/* sctime_readout: spacecraft clock of first minor frame of the */
/* first edb of the sectored rate output cycle */

/* sctime_collection:  time of the start of the first spin in the */
/* collection cycle, in spacecraft clock time units */

/* ssector structure contains basic rates for 1 10-spin collection cycle */

struct ssector{

   uint32 sctime_readout;	/* 32 bit spacecraft time  */
   float64 sctime_collection; /* spacecraft time, sub-second resolution */
   uint32 QAC;	/* Number of missing frames in this 10-spin cycle */

   uint16 SECTOR[SSEC_N][SSEC_S]; /* 20 Sectored rates, 8 sectors */
};

s3_sbasic.h , v 1.6

#include "hdfi.h"

/* SEPICA Basic rates */

#define SBAS_N     16  /* number of basic rates */
#define SBAS_S     8  /* number of sectors */
#define SBAS_CYC   12  /* number of cycles per SR = 60 / 5 */
#define SBAS_NFILL 2  /* amount of fill data per cycle */

 /* total size (in bytes) of SBAS data (including slack) in a full SR */
#define SBAS_TSZ   2340  

 /* size (in bytes) of SMON cycle (including slack) */
#define SBAS_CSZ   SBAS_TSZ/SBAS_CYC 
#define SBAS_ESZ   SBAS_TSZ/60  /* size (in bytes) of SBAS area in EDB */

/* Basic rates are collected over 5 spins and output during the next */
/* 5 spins(or edb's). There are 12 basic rate collection cycles per */
/* Science Record */

/* sctime_readout: spacecraft clock of first minor frame of the */
/* first edb of the basic rate output cycle */

/* sctime_collection:  time of the start of the first spin in the */
/* collection cycle, in spacecraft clock time units */

/* sbasic structure contains basic rates for 1 5-spin collection cycle */
struct sbasic{

   uint32 sctime_readout;	/* 32 bit spacecraft time  */
   float64 sctime_collection; /* spacecraft time, sub-second resolution */
   uint32 QAC;	/* number of frames of missing data in this 5-spin cycle */

   uint16 BASIC[SBAS_N][SBAS_S];/* 16 Basic rates, 8 sectors */
   uint16 FILL[SBAS_NFILL];    /*  Fill data  */
};

s3_sstatus.h , v 1.3

#include "hdfi.h"

/* sctime_readout: scclock of first minor frame of Science Record */

struct sstatus{
	uint32 sctime_readout;	/* 32 bit spacecraft time  */

	uint32 QAC;	/* number of missing frames in this SR */
	uint8  QACarr[720]; /* array of flags indicating which minor frames */
	                    /* in the SR are missing. 0=OK, 1=missing */

	uint16 STACMD[60];  /* Command bytes */
	uint32 STARET[60];  /* Return bytes */
};

s3_spha.h , v 1.6

#include "hdfi.h"

#define SEP_PHA_MAX 30     /* the maximum number of pha events that fit */
                           /* into this data structure - an arbitrary number */

#define SEP_PHA_CYCPERSR 60 /* number of pha collection cycles per Science Rec */

/* sctime_readout: spacecraft clock of first minor frame of the EDB */

/* sctime_collection: pha data are collected over 1 spin and output */
/* during the next spin. There are 60 pha collection cycles per SR. */
/* sctime_collection contains the time of the start of the */
/* collection cycle (spin), in spacecraft clock time units */

struct spha{
	uint32 sctime_readout;	   /* 32 bit spacecraft time  */
	float64 sctime_collection; /* spacecraft time, sub-second resolution */

	uint16 QAC;	/* number of frames missing in this EDB */

	uint16  concat; /* Sequence number for this structure will be */
		        /* greater than 1 for cases where the number of */
		        /* events in the EDB exceeds SEP_PHA_MAX. In these */
		        /* cases, concat will count down from N to 1, where N */
			/* is the total number of spha structures for the */
			/* current EDB. */

	uint16 numevts; /* Number of pha events in this data structure. */
                        /* Should be SEP_PHA_MAX when concat > 1. */
			/* When concat == 1, numevts <= SEP_PHA_MAX */

	uint16 numevtsedb; /* Number of pha events in the whole EDB */

	uint16 edb; /* sequence number of EDB in Science Record (0-59) */
	
	uint8  range[SEP_PHA_MAX]; /* range*/
	uint8  sector[SEP_PHA_MAX];/* sector*/
	uint8  fan[SEP_PHA_MAX];   /* fan */
	uint8  sys[SEP_PHA_MAX];   /* sys*/
	uint8  dZ[SEP_PHA_MAX];    /*  delta Z */
	uint16 E[SEP_PHA_MAX];     /* Energy*/
	uint8  Eg[SEP_PHA_MAX];    /* Energy gain bit */
	uint16 dE[SEP_PHA_MAX];    /* delta Energy */
	uint8  dEg[SEP_PHA_MAX];   /* delta Energy gain bit*/
	uint16 Y[SEP_PHA_MAX];     /* Y value */
};

s3_sdiag.h , v 1.4

#include "hdfi.h"

#define SEP_DIAG_CYCLEN    88 

#define SEP_DIAG_CYCPERSR  60  /* number of diag collection cycles per Science Rec */

/* sctime_readout: spacecraft clock of first minor frame of the EDB */

/* sctime_collection: diag data are collected over 1 spin and output */
/* during the next spin. There are 60 diag collection cycles per SR. */
/* sctime_collection contains the time of the start of the  */
/* collection cycle (spin), in spacecraft clock time units */


struct sdiag{
	uint32 sctime_readout;	/* 32 bit spacecraft time  */
	float64 sctime_collection; /* spacecraft time, sub-second resolution */

	uint16 QAC;	/* number of missing frames in this EDB */

	uint16  concat; /* Sequence number for this structure will be */
		        /* greater than 1 for cases where the number of */
		        /* events in the EDB exceeds SEP_PHA_MAX. In these */
                        /* cases, concat will count down from N to 1, where N */
                        /* is the total number of spha structures for the */
                        /* current EDB. */

	uint16 numevts; /* Number of diag events in this structure. */
                        /* Should be SEP_DIAG_MAX when concat > 1. */
                        /* When concat == 1, numevts <= SEP_DIAG_MAX */
			
        uint16 numevtsedb; /* Number of diag events in the whole EDB */
	
	uint16 edb; /* sequence number of EDB in Science Record (0-59) */

	uint16 DIAG[4][SEP_DIAG_CYCLEN]; /* engineering data */
};

sepica_rwbr.h , v 1.3

#include "hdfi.h"

#define SEP_GEOMFAC .18   /* cm2 - sr */

struct Sepica_rwbr
{
  float64 bin_start;  /* beginning of bin. # of sec since Jan 1 1996 UTC */
  float64 bin_end;  /* end of bin. # of sec since Jan 1 1996 UTC */

    /* rate for indicated channel, negative values indicate */
    /* missing data */
    float32 H_lo;             /* low Energy (0.1-0.8 Mev/n) H channel */
    float32 H_hi;             /* high Energy (0.8-9.0 Mev/n) H channel */
    float32 He_lo;            /* low Energy (0.025-0.75 MeV/n) He channel */
    float32 He_hi;            /* high Energy (0.75-14 MeV/n) He channel */
    float32 C;                /* (1.5-25 MeV/n) C channel */
    float32 O;                /* (1.12-18.8 MeV/n) O channel */
    float32 Mg_Si;            /* (0.7-11.5 MeV/n) Mg,Si channel */
    float32 Fe;               /* (0.35-5.75 MeV/n) Fe channel */

    float32 livetime;       /* livetime for this cycle */
};

s3_dspare_class.h , v 1.2


#include "hdfi.h"

#define SBITABLEITEMS 256
#define SRCTABLEITEMS 256
#define SDETABLEITEMS 480
#define SCOSITEMS 16
#define SCOS2ITEMS 32
#define SLNDEITEMS 36
#define SLNEITEMS 32
#define SYITEMS 20
#define SPSEQITEMS 31

struct s3s_dspare_class {

uint32 sctime; /* 32bit spacecraft time */

uint8 sbitable[SBITABLEITEMS];
uint8 srctable[SRCTABLEITEMS];
uint8 sdetable[SDETABLEITEMS];
uint8 scos[SCOSITEMS];
uint8 scos2[SCOS2ITEMS];

int16 SlndE_Emin0;
int16 SlndE_Emin1;
float32 SlndE_MinClass;
float32 SlndE_MaxClass;
float32 SlndE_Eoffset0;
float32 SlndE_Eoffset1;
float32 SlndE_E00;
float32 SlndE_E01;
float32 SlndE_E1;
float32 SlndE_Cosine;

int16 SlnE_Emin0;
int16 SlnE_Emin1;
float32 SlnE_MinClass;
float32 SlnE_MaxClass;
float32 SlnE_Eoffset0;
float32 SlnE_Eoffset1;
float32 SlnE_E00;
float32 SlnE_E01;
float32 SlnE_E1;

int16 SY_focal;
float32 SY_Cosine;
float32 SY_Y1;
int16 SQ_MaxQ;
float32 SQ_Q10;
float32 SQ_Q11;

uint8 spseq[SPSEQITEMS];

};



















s3_dspare_cmd.h , v 1.3


#include "hdfi.h"

#define SCOMMANDITEMS 55

struct s3s_dspare_cmd {

uint32 sctime; /* 32bit spacecraft time */

/* SEPICA Command parameters, from EDB's 0,20,40 */
int16 SCommand1[SCOMMANDITEMS];
int16 SCommand2[SCOMMANDITEMS];
int16 SCommand3[SCOMMANDITEMS];

/* some unique SEPICA command parameters pulled from the above arrays */
int16 Pressure_set_1[3];    /* pressure */
int16 Pressure_set_2[3];    /* pressure */
int16 Pressure_set_3[3];    /* pressure */
int16 HvEnable[3];	    /* HV enables */
int16 BITChannel_1[3];	    /* BIT channel */
int16 BITChannel_2[3];	    /* BIT channel */
int16 BITChannel_3[3];	    /* BIT channel */
int16 DAC0Channel_1[3];     /* DAC 0 channel */
int16 DAC0Channel_2[3];     /* DAC 0 channel */
int16 DAC0Channel_3[3];     /* DAC 0 channel */
int16 DAC1Channel_1[3];     /* DAC 1 channel */
int16 DAC1Channel_2[3];     /* DAC 1 channel */

};

s3_dspare_contr.h , v 1.3


#include "hdfi.h"

struct s3s_dspare_contr{

uint32 sctime;             /* 32bit spacecraft time */

/* SEPICA control words, from EDB's 3,23,43 */
int16 Mode[3];		   /* mode */
int16 Delay[3];		   /* power off delay */
int16 Lim30k[3];	   /* 30 kV limit/delta */
int16 Lim30k_delta[3];
int16 Lim2k[3];		   /* 2 kV limit/delta */
int16 Lim2k_delta[3];
int16 Lim75[3];		   /* 75 V limit/delta */
int16 Lim75_delta[3];
int16 PhaThres_low[3];	   /* PHA threshold */
int16 PhaThres_hi[3];		
int16 PressCtrl_1[3];	   /* pressure control */
int16 PressCtrl_2[3];
int16 PressCmd_1[3];	   /* pressures */
int16 PressCmd_2[3];
int16 PressCmd_3[3];

int16 Mode_Cmd[3];
int16 Delay_Cmd[3];
int16 Lim30k_Cmd[3];
int16 Lim30k_delta_Cmd[3];
int16 Lim2k_Cmd[3];
int16 Lim2k_delta_Cmd[3];
int16 Lim75_Cmd[3];
int16 Lim75_delta_Cmd[3];
int16 PhaThres_low_Cmd[3];
int16 PhaThres_hi_Cmd[3];
int16 PressCtrl_1_Cmd[3];
int16 PressCtrl_2_Cmd[3];
int16 PressCmd_1_Cmd[3];
int16 PressCmd_2_Cmd[3];
int16 PressCmd_3_Cmd[3];
};







s3_dspare_alarm.h , v 1.3


#include "hdfi.h"

struct s3s_dspare_alarm {

uint32 sctime; /* 32bit spacecraft time */

/* SEPICA limits for alarm monitoring, from EDB 6 */
uint16 AlarmDelay_set;	/* delay 10 min. */
uint16 AlarmDis;	/* 30kV discharge check */
uint16 AlarmPres;	/* pressure check */
uint16 AlarmLV;		/* LV status bit check */
uint16 AlarmV1Open_set;	/* valve 1 open */
uint16 AlarmV2Open_set;	/* valve 2 open */
uint16 AlarmV3Open_set;	/* valve 3 open */
uint16 AlarmPC1P_min;	/* PC1 pressure */
uint16 AlarmPC1P_max;	/* PC1 pressure */
uint16 AlarmPC2P_min;	/* PC2 pressure */
uint16 AlarmPC2P_max;	/* PC2 pressure */
uint16 AlarmPC3P_min;	/* PC3 pressure */
uint16 AlarmPC3P_max;	/* PC3 pressure */
uint16 AlarmP5V_min;	/* +5V */
uint16 AlarmP5V_max;	/* +5V */
uint16 AlarmP5I_min;	/* +5V (I) */
uint16 AlarmP5I_max;	/* +5V (I) */
uint16 AlarmM5V_min;	/* -5V */
uint16 AlarmM5V_max;	/* -5V */
uint16 AlarmM5I_min;	/* -5V (I) */
uint16 AlarmM5I_max;	/* -5V (I) */
uint16 AlarmP15V_min;	/* +15V */
uint16 AlarmP15V_max;	/* +15V */
uint16 AlarmP15I_min;	/* +15V (I) */
uint16 AlarmP15I_max;	/* +15V (I) */
uint16 AlarmM15V_min;	/* -15V */
uint16 AlarmM15V_max;	/* -15V */
uint16 AlarmM15I_min;	/* -15V (I) */
uint16 AlarmM15I_max;	/* -15V (I) */
uint16 Alarm75V_min;	/* 75V */
uint16 Alarm75V_max;	/* 75V */
uint16 Alarm75I_min;	/* 75V (I) */
uint16 Alarm75I_max;	/* 75V (I) */
uint16 Alarm2kV_min;	/* 2kV */
uint16 Alarm2kV_max;	/* 2kV */
uint16 Alarm2kI_min;	/* 2kV (I) */
uint16 Alarm2kI_max;	/* 2kV (I) */
uint16 Alarm2kAV_min;	/* 2kV A */
uint16 Alarm2kAV_max;	/* 2kV A */
uint16 Alarm2kBV_min;	/* 2kV B */
uint16 Alarm2kBV_max;	/* 2kV B */
uint16 Alarm2kCV_min;	/* 2kV C */
uint16 Alarm2kCV_max;	/* 2kV C */
uint16 Alarm30kV_min;	/* 30kV */
uint16 Alarm30kV_max;	/* 30kV */
uint16 Alarm30kI_min;	/* 30kV (I) */
uint16 Alarm30kI_max;	/* 30kV (I) */
uint16 AlarmDisV_min;	/* 30kV discharge */
uint16 AlarmDisV_max;	/* 30kV discharge */
uint16 AlarmDisI_min;	/* 30kV discharge (I) */
uint16 AlarmDisI_max;	/* 30kV discharge (I) */
};











s3_dspare_alarmcnt.h , v 1.3


#include "hdfi.h"

struct s3s_dspare_alarmcnt {

uint32 sctime; /* 32bit spacecraft time */

/* SEPICA counters for alarm violations, from EDB 7 */

uint8 AlarmDelay_set_Cnt;	/* delay 10 min. */
uint8 AlarmDis_Cnt;		/* 30kV discharge check */
uint8 AlarmPres_Cnt;		/* pressure check */
uint8 AlarmLV_Cnt;		/* LV status bit check */
uint8 AlarmV1Open_set_Cnt;	/* valve 1 open */
uint8 AlarmV2Open_set_Cnt;	/* valve 2 open */
uint8 AlarmV3Open_set_Cnt;	/* valve 3 open */
uint8 AlarmPC1P_min_Cnt;	/* PC1 pressure */
uint8 AlarmPC1P_max_Cnt;	/* PC1 pressure */
uint8 AlarmPC2P_min_Cnt;	/* PC2 pressure */
uint8 AlarmPC2P_max_Cnt;	/* PC2 pressure */
uint8 AlarmPC3P_min_Cnt;	/* PC3 pressure */
uint8 AlarmPC3P_max_Cnt;	/* PC3 pressure */
uint8 AlarmP5V_min_Cnt;	        /* +5V */
uint8 AlarmP5V_max_Cnt;   	/* +5V */
uint8 AlarmP5I_min_Cnt;	        /* +5V (I) */
uint8 AlarmP5I_max_Cnt;	        /* +5V (I) */
uint8 AlarmM5V_min_Cnt;	        /* -5V */
uint8 AlarmM5V_max_Cnt;	        /* -5V */
uint8 AlarmM5I_min_Cnt;    	/* -5V (I) */
uint8 AlarmM5I_max_Cnt;	        /* -5V (I) */
uint8 AlarmP15V_min_Cnt;	/* +15V */
uint8 AlarmP15V_max_Cnt;	/* +15V */
uint8 AlarmP15I_min_Cnt;	/* +15V (I) */
uint8 AlarmP15I_max_Cnt;	/* +15V (I) */
uint8 AlarmM15V_min_Cnt;	/* -15V */
uint8 AlarmM15V_max_Cnt;	/* -15V */
uint8 AlarmM15I_min_Cnt;	/* -15V (I) */
uint8 AlarmM15I_max_Cnt;	/* -15V (I) */
uint8 Alarm75V_min_Cnt;		/* 75V */
uint8 Alarm75V_max_Cnt;		/* 75V */
uint8 Alarm75I_min_Cnt;		/* 75V (I) */
uint8 Alarm75I_max_Cnt;		/* 75V (I) */
uint8 Alarm2kV_min_Cnt;		/* 2kV */
uint8 Alarm2kV_max_Cnt;		/* 2kV */
uint8 Alarm2kI_min_Cnt;		/* 2kV (I) */
uint8 Alarm2kI_max_Cnt;		/* 2kV (I) */
uint8 Alarm2kAV_min_Cnt;	/* 2kV A */
uint8 Alarm2kAV_max_Cnt;	/* 2kV A */
uint8 Alarm2kBV_min_Cnt;	/* 2kV B */
uint8 Alarm2kBV_max_Cnt;	/* 2kV B */
uint8 Alarm2kCV_min_Cnt;	/* 2kV C */
uint8 Alarm2kCV_max_Cnt;	/* 2kV C */
uint8 Alarm30kV_min_Cnt;	/* 30kV */
uint8 Alarm30kV_max_Cnt;	/* 30kV */
uint8 Alarm30kI_min_Cnt;	/* 30kV (I) */
uint8 Alarm30kI_max_Cnt;	/* 30kV (I) */
uint8 AlarmDisV_min_Cnt;	/* 30kV discharge */
uint8 AlarmDisV_max_Cnt;	/* 30kV discharge */
uint8 AlarmDisI_min_Cnt;	/* 30kV discharge (I) */
uint8 AlarmDisI_max_Cnt;	/* 30kV discharge (I) */
};














For comments, questions or suggestions regarding these data structures,
email: asc@srl.caltech.edu
Last update: Wed Nov 3 12:45:32 PST 1999